The embodiments herein generally relate to verification of integrated chips, and more particularly to a computer-implemented verification system for performing a system level verification or a system on chip level verification of integrated circuits.
Typically, a hardware system comprises of multiple functional units connected to one another via a common interconnect (termed as bus-fabric). The functional units may be designed so as to achieve a variety of functionalities/objectives. Many of the functional units may have multiple configuration settings resulting in varied functionality of the hardware system as a whole. Pursuant to an exemplary scenario, the hardware system as a whole may need to be verified for functionality and performance goals, through a process termed as functional verification. Functional verification is an important process in development of an Integrated Circuit (IC) & involves almost 50-70% of project time and is widely acknowledged to be a bottleneck in the development time with major investment in time and resources. The motivation for the functional verification process is to constantly track the design changes/modifications against the original specifications and usually requires an executable model of the design that eventually translates into an IC product.
The functional verification process tries to find deviations in design implementation (design flaws) that are contrary to a specification. The functional verification process involves executing a large number of tests usually generated by random test generators on the executable model & comparing them against expected outputs in conformance with specifications. Currently, in system-On-Chip (SOC) methodology, majority of designs have at least one embedded central processing unit (CPU) core to execute software so as to enable, disable or change the functionality of underneath hardware as demanded by applications reacting to system conditions or user inputs.
The SOC methodology hinges on vendors integrating pre-verified functional units or design Intellectual Properties (IPs) from trusted IP-vendors based on standard bus protocols to create a functional system and defers detection of system-level issues to integration time at the cost of SOC vendor's time-to-market (TTM). With ever-crunching TTM it becomes imperative for SOC vendors to detect system-level issues early in verification flow. The current trend of placing much of hardware features under the control of the software makes the SOC verification process to view a system-under-test as a combination of software and hardware. This makes the process of verification complex and extended as it imposes software to be included and available during the process.
At system-level much of the verification emphasis is on interaction between functional units (or design-IPs) over common bus interconnects. System-level bugs arise from the interaction themselves and not in the design-IP functionality itself. Since the system as a whole is intended to support heterogeneous interactions among design-IPs concurrently, it places system-level resources and logic under strain. Much of system-level issues can be attributed to concurrency in interactions and can be dormant if not stimulated well. Hence much of the system-level verification effort focuses on placing the system-under test around a test bench and carefully orchestrating concurrency in interactions in the system. Effective system-level verification involves placing the SOC in a verification environment which provides the means to observe, and verify interaction issues.
Current verification techniques involve conversion of a system-level scenario of interest into directed test-software and test-bench components through manual development. Directed test-software executing on the embedded core in conjunction with constrained random techniques used on test bench components are prevalent today. Manual development of directed software and relevant test-bench components for individual scenarios is not a scalable approach. As mentioned earlier, to detect hard-to-find bugs it is important to increase concurrency in interactions. This implies combining multiple scenarios which can be played out concurrently on the system-under-test. This approach makes it difficult for verification process to scale on increasing interaction. Accordingly, there remains a need for system for test software generation based on system-level scenario in specification form for functional verification of system-on-chip on simulation and emulation platforms.